So, how does make accomplish its magical feats? By using a makefile, which contains rules that tell
make what to build and how to build it. A rule consists of the following:
Target: The ???thing??? make ultimately tries to create
Dependencies: A list of one or more dependencies (usually files) required to build
the target
Commands: A list of commands to execute to create the target from the specified
dependencies
Makefiles constitute a database of dependency information for the programs they build and automatically
verify that all of the files necessary for building a program are available.
When invoked, GNU make looks for a file named GNUmakefile, makefile, or Makefile, in
that order. For some reason, most developers use the last form, Makefile. Makefile rules have the
general form
target : dependency dependency [...]
command
command
[...]
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Programming in Linux Part VI
In this syntax, target is usually the file, such as a binary or object file, to create. dependency is a
list of one or more files required as input to create target. Each command is a step such as a compiler
invocation or a shell command that is necessary to create target. Unless specified otherwise,
make does all of its work in the current working directory.
The first character in a command must be the tab character; eight spaces will not suffice.
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